In the microelectronics industry, pattern density shrinks have enabled significant performance gains and continue to occur in the predictable 2 year cycle according to Moore's Law. In order to maintain or improve the operations of a device, both transistor and interconnect level changes have been made. More specifically focusing on the interconnect structures (commonly referred to as the back-end-of line, BEOL), the dimensional shrink has caused a transition from aluminum to copper metallization in order to maintain tolerable line resistances. In order to maintain adequate capacitance between copper lines, the dielectric or insulating films that enclose the copper lines have also changed to compensate for the integration changes necessary for the patterning changes. In order to minimize capacitance of the insulating films, the dielectric constant (k) of each dielectric should ideally be continually reduced. For the interlevel dielectrics (“ILD”), this transition has continually occurred from silicon dioxide to fluorosilicate glass to dense organosilicate glass and finally to porous organosilicate glass with k values of 4.0, 3.3-3.7, 2.7-3.1, and <2.6, respectively.
Typically, the ILD insulating films can retain moisture in the dielectrics. Given that copper is susceptible to rapid oxidation that can cause reliability issues, barrier dielectrics comprise a portion of the dielectric stack to serve as a diffusion barrier between the copper lines and ILD films, preventing diffusion of water from the ILD onto the copper surface and preventing copper diffusion into the ILD films. Contrary to the trends for ILD films, the barrier dielectrics have not scaled significantly, due to the reliability functions that the dielectrics serve within the interconnect structure. However, given the disproportionate scaling in dielectric constant of the ILD films relative to the barrier dielectrics, the capacitance contribution of the barriers now is more significant to the overall capacitance of the interconnect structure than in previous technology nodes.
Other semiconductor applications, such as photovoltaics and thin-film display devices, also have requirements for lower k value dielectric barrier films. In these applications, the need for copper diffusion properties is not needed but there are other additional requirements such as transparency, wet chemical resistance and high mechanical strength. In addition, the ability to tune the dielectric properties for density, refractive index, film composition and electrical properties is a necessity.
In this invention, plasma enhanced chemical vapor deposition (PECVD) processes with incorporation of siloxane precursors provide dielectric films with dielectric constants that are significantly lower than current barrier dielectric films while still maintaining adequate barrier properties. The current industry standard precursors, 3MS (trimethylsilane) or 4MS (tetramethylsilane), provide good properties but are difficult to reduce their dielectric constants.
The prior art calls out specific process conditions for alkylalkoxysilanes that provide lower dielectric constants. Under these situations, residence times of the reaction gases in the chamber are >100 ms in order to provide sufficient reactivity for the gases in order to get linear siloxane films. The prior art also suggests that it is desired to have lower dielectric constants below 3.1 and that this is achieved by increasing the residence time of the precursor in the chamber.
Prior art relevant to the field of this invention includes: US2006/0251876A1, U.S. Pat. No. 6,383,955, and US2001/0021590.